[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Cliff Huang, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai.
Hello Tim Crawford, build bot (Jenkins), Cliff Huang, Cliff Huang, Subrata Banik, Maulik V Vaghela, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/60179

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function
......................................................................

soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() function

The PMC IPC method used to enable/disable PCIe clk sources uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.

BUG=b:197983574

Signed-off-by: Tim Wawrzynczak 
Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d
---
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
M src/soc/intel/tigerlake/pcie_rp.c
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/60179/3