Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13536
-gerrit
commit 42fe2fedaa7fea30d293aa205065f4f2f3e82c53 Author: Vladimir Serbinenko phcoder@gmail.com Date: Sun Jan 31 12:42:26 2016 +0100
stout: Switch to native raminit
Teseted at FOSDEM.
Change-Id: I622e2b4adc1d5c623d57f1d741a96073c1efb5d5 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/google/stout/Makefile.inc | 2 + src/mainboard/google/stout/devicetree.cb | 2 + src/mainboard/google/stout/gpio.c | 288 +++++++++++++++++++++++++++++++ src/mainboard/google/stout/gpio.h | 288 ------------------------------- src/mainboard/google/stout/romstage.c | 206 +++++----------------- 6 files changed, 336 insertions(+), 452 deletions(-)
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 0e85a34..0827279 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 256948d..31281be 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ##
+romstage-y += gpio.c + ramstage-y += ec.c
romstage-y += chromeos.c diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 8c579d6..37d1ae6 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610"
+ register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c new file mode 100644 index 0000000..7fffe8b --- /dev/null +++ b/src/mainboard/google/stout/gpio.c @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STOUT_GPIO_H +#define STOUT_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ + .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ + .gpio2 = GPIO_MODE_NONE, /* NOT USED */ + .gpio3 = GPIO_MODE_NONE, /* NOT USED */ + .gpio4 = GPIO_MODE_NONE, /* NOT USED */ + .gpio5 = GPIO_MODE_GPIO, /* INTH# */ + .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ + .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ + .gpio8 = GPIO_MODE_NONE, /* NOT USED */ + .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ + .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ + .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ + .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ + .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ + .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ + .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ + .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ + .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ + .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ + .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ + .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ + .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ + .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ + .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ + .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ + .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ + .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ + .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ + .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ + .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ + .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + + .gpio19 = GPIO_DIR_OUTPUT, + + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + + .gpio19 = GPIO_LEVEL_LOW, + + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ + .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ + .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ + .gpio36 = GPIO_MODE_NONE, /* NOT USED */ + .gpio37 = GPIO_MODE_NONE, /* NOT USED */ + .gpio38 = GPIO_MODE_NONE, /* NOT USED */ + .gpio39 = GPIO_MODE_NONE, /* NOT USED */ + .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ + .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ + .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ + .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ + .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ + .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ + .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ + .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ + .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ + .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ + .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ + .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ + .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ + .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ + .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ + .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ + .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ + .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ + .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ + .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + + .gpio51 = GPIO_DIR_OUTPUT, + + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + + .gpio57 = GPIO_DIR_INPUT, + + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_LOW, + + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + + .gpio51 = GPIO_LEVEL_HIGH, + + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + + .gpio57 = GPIO_LEVEL_LOW, + + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ + .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ + .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ + .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ + .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ + .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ + .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ + .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ + .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ + .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ + .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ + .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h deleted file mode 100644 index f992013..0000000 --- a/src/mainboard/google/stout/gpio.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STOUT_GPIO_H -#define STOUT_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ - .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ - .gpio2 = GPIO_MODE_NONE, /* NOT USED */ - .gpio3 = GPIO_MODE_NONE, /* NOT USED */ - .gpio4 = GPIO_MODE_NONE, /* NOT USED */ - .gpio5 = GPIO_MODE_GPIO, /* INTH# */ - .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ - .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ - .gpio8 = GPIO_MODE_NONE, /* NOT USED */ - .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ - .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ - .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ - .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ - .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ - .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ - .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ - .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ - .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ - .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ - .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ - .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ - .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ - .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ - .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ - .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ - .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ - .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ - .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ - .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_OUTPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_OUTPUT, - - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_OUTPUT, - .gpio17 = GPIO_DIR_OUTPUT, - - .gpio19 = GPIO_DIR_OUTPUT, - - .gpio21 = GPIO_DIR_OUTPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_OUTPUT, - - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, - - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_LOW, - - .gpio19 = GPIO_LEVEL_LOW, - - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_LOW, - .gpio23 = GPIO_LEVEL_LOW, - - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_HIGH, - .gpio29 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ - .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ - .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ - .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ - .gpio36 = GPIO_MODE_NONE, /* NOT USED */ - .gpio37 = GPIO_MODE_NONE, /* NOT USED */ - .gpio38 = GPIO_MODE_NONE, /* NOT USED */ - .gpio39 = GPIO_MODE_NONE, /* NOT USED */ - .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ - .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ - .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ - .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ - .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ - .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ - .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ - .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ - .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ - .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ - .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ - .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ - .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ - .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ - .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ - .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ - .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ - .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ - .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ - .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ - .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ - .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - - .gpio51 = GPIO_DIR_OUTPUT, - - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - - .gpio57 = GPIO_DIR_INPUT, - - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_HIGH, - .gpio35 = GPIO_LEVEL_HIGH, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, - .gpio41 = GPIO_LEVEL_LOW, - - .gpio48 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_HIGH, - - .gpio51 = GPIO_LEVEL_HIGH, - - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_LOW, - - .gpio57 = GPIO_LEVEL_LOW, - - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ - .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ - .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ - .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ - .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ - .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ - .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ - .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ - .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ - .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ - .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ - .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio64 = GPIO_DIR_OUTPUT, - .gpio65 = GPIO_DIR_OUTPUT, - .gpio66 = GPIO_DIR_OUTPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_OUTPUT, - .gpio70 = GPIO_DIR_OUTPUT, - .gpio71 = GPIO_DIR_OUTPUT, - .gpio72 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio64 = GPIO_LEVEL_HIGH, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_HIGH, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_HIGH, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map stout_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 030dee7..6860279 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -27,14 +27,11 @@ #include <cbmem.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <bootmode.h> #include <tpm.h> #include <cbfs.h> @@ -42,7 +39,7 @@ #include "ec.h" #include "onboard.h"
-static void pch_enable_lpc(void) +void pch_enable_lpc(void) { /* * Enable: @@ -51,14 +48,14 @@ static void pch_enable_lpc(void) * PS/2 Keyboard/Mouse Port60/64 * FDD Port3F0h-3F5h and Port3F7h */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - CNF1_LPC_EN | FDD_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_EN, + KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | FDD_LPC_EN);
/* Stout EC Decode Range Port68/6C */ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001)); }
-static void rcba_config(void) +void rcba_config(void) { u32 reg32;
@@ -77,13 +74,13 @@ static void rcba_config(void)
/* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); + (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | + (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | + (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); @@ -103,7 +100,7 @@ static void rcba_config(void) /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void)RCBA16(OIC);
/* Disable unused devices (board specific) */ reg32 = RCBA32(FD); @@ -113,22 +110,34 @@ static void rcba_config(void) RCBA32(FD) = reg32; }
-// FIXME, this function is generic code that should go to sb/... or -// nb/../early_init.c -static void early_pch_init(void) -{ - // Nothing to do for stout -} +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled usb oc pin length */ + {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, 0, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {0, 0, 0}, /* P8: Empty */ + {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, /* P10: Empty */ + {0, 0, 0}, /* P11: Empty */ + {0, 0, 0}, /* P12: Empty */ + {1, 0, -1}, /* P13: Bluetooth (no OC) */ + +};
- /* - * The Stout EC needs to be reset to RW mode. It is important that - * the RTC_PWR_STS is not set until ramstage EC init. - */ +/* + * The Stout EC needs to be reset to RW mode. It is important that + * the RTC_PWR_STS is not set until ramstage EC init. + */ static void early_ec_init(void) { u8 ec_status = ec_read(EC_STATUS_REG); - int rec_mode = IS_ENABLED(CONFIG_BOOTMODE_STRAPS) && - get_recovery_mode_switch(); + int rec_mode = + IS_ENABLED(CONFIG_BOOTMODE_STRAPS) && get_recovery_mode_switch();
if (((ec_status & 0x3) == EC_IN_RO_MODE) || ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) { @@ -138,7 +147,8 @@ static void early_ec_init(void) /* * Tell EC to exit RO mode */ - printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n"); + printk(BIOS_DEBUG, + "EC will exit RO mode and boot normally\n"); ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK); die("wait for ec to reset"); } @@ -148,145 +158,15 @@ static void early_ec_init(void) } }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_early_init(int s3resume) { - int boot_mode = 0; - int cbmem_was_initted; - - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ - { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ - { 0, 1, 0x0000 }, /* P2: Empty */ - { 1, 1, 0x0040 }, /* P3: Camera (no OC) */ - { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */ - { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */ - { 0, 1, 0x0000 }, /* P6: Empty */ - { 0, 1, 0x0000 }, /* P7: Empty */ - { 0, 5, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */ - { 0, 5, 0x0000 }, /* P10: Empty */ - { 0, 5, 0x0000 }, /* P11: Empty */ - { 0, 5, 0x0000 }, /* P12: Empty */ - { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ - }, - .usb3 = { - .mode = XHCI_MODE, - .hs_port_switch_mask = XHCI_PORTS, - .preboot_support = XHCI_PREBOOT, - .xhci_streams = XHCI_STREAMS, - }, - }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&stout_gpio_map); - - /* Initialize console device(s) */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - halt(); - } - - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - boot_mode = southbridge_detect_s3_resume() ? 2 : 0; - /* Do ec reset as early as possible, but skip it on S3 resume */ - if (boot_mode < 2) + if (!s3resume) early_ec_init(); +}
- post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x39); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(&pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3b); - /* Perform some initialization that must run before stage2 */ - early_pch_init(); - post_code(0x3c); - - rcba_config(); - post_code(0x3d); - - quick_ram_check(); - post_code(0x3e); - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); - - if (boot_mode==2 && !cbmem_was_initted) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - northbridge_romstage_finalize(boot_mode==2); - - post_code(0x3f); - if (CONFIG_LPC_TPM) { - init_tpm(boot_mode == 2); - } +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); }