[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism

[Lawrence Chang (Code Review)]

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Nick Vaccaro, Paul Menzel, Simon Yang.

Lawrence Chang has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email )

Change subject: soc/intel/jasperlake: add support for RP LTR mechanism
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84866/comment/f516a348_f6ba310a?usp... :
PS3, Line 13: Tested on Awasuki with RTL8852BE
> How to check this exactly? coreboot logs or `lspci`?

You can check root port configuration space dump, LTR Mechanism Enable bit is offset 68h[10].