[coreboot-gerrit] Change in ...coreboot[master]: mediatek/mt8183: Enable RTC eosc calibration feature to save power

[Ran Bi (Code Review)]

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32339

Change subject: mediatek/mt8183: Enable RTC eosc calibration feature to save power
......................................................................

mediatek/mt8183: Enable RTC eosc calibration feature to save power

When system shutdown, RTC enable eosc calibration feature to save
power. Then coreboot RTC driver need to call rtc_enable_dcxo function
at every boot up to switch RTC clock source to a more accurate one.

BUG=b:128467245
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748
Signed-off-by: Ran Bi 
---
M src/soc/mediatek/mt8183/rtc.c
1 file changed, 4 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/32339/1

diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 62256eb..ba05f86 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -197,12 +197,6 @@
    	goto err;
    }

-	/* using dcxo 32K clock */
-	if (!rtc_enable_dcxo()) {
-		ret = -RTC_STATUS_OSC_SETTING_FAIL;
-		goto err;
-	}
-
    if (recover)
    	mdelay(20);

@@ -311,6 +305,10 @@
    pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
    pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);

+	/* using dcxo 32K clock */
+	if (!rtc_enable_dcxo())
+		rtc_info("rtc_enable_dcxo() fail\n");
+
    rtc_boot_common();
    rtc_bbpu_power_on();
 }