Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58370 )
Change subject: soc/amd/stoneyridge/include/iomap: rename I2C[ABCD]_BASE_ADDRESS defines ......................................................................
soc/amd/stoneyridge/include/iomap: rename I2C[ABCD]_BASE_ADDRESS defines
Picasso and Cezanne define and use APU_I2C[01234]_BASE for the base addresses of the I2C controllers, so align Stoneyridge with this. The ACPI device names aren't changed from I2C[ABCD] to I2C[0123] for now since this might change behavior in the OS and would also change the resulting binary of a timeless build.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I9c400c073eba5c14bd35703b717f75df89a8719d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58370 Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/kahlee/variants/treeya/audio.c M src/soc/amd/stoneyridge/acpi/sb_fch.asl M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/i2c.c M src/soc/amd/stoneyridge/include/soc/iomap.h 5 files changed, 17 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/treeya/audio.c b/src/mainboard/google/kahlee/variants/treeya/audio.c index 1c7a4c4..ac7f7a2 100644 --- a/src/mainboard/google/kahlee/variants/treeya/audio.c +++ b/src/mainboard/google/kahlee/variants/treeya/audio.c @@ -23,7 +23,7 @@ printk(BIOS_INFO, "Checking audio codec\n"); return; } - } while (mmio_dev->path.mmio.addr != I2CA_BASE_ADDRESS); + } while (mmio_dev->path.mmio.addr != APU_I2C0_BASE);
while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { if (child->path.type != DEVICE_PATH_I2C) diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index b389c66..212a111 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -74,7 +74,7 @@ Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 3 } - Memory32Fixed (ReadWrite, I2CA_BASE_ADDRESS, 0x1000) + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) })
Method (_STA, 0x0, NotSerialized) @@ -90,7 +90,7 @@ Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, I2CB_BASE_ADDRESS, 0x1000) + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { @@ -104,7 +104,7 @@ Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed (ReadWrite, I2CC_BASE_ADDRESS, 0x1000) + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) })
Method (_STA, 0x0, NotSerialized) @@ -119,7 +119,7 @@ Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, I2CD_BASE_ADDRESS, 0x1000) + Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index fbf205e..5cc52b6 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -101,10 +101,10 @@ static void set_mmio_dev_ops(struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - case I2CB_BASE_ADDRESS: - case I2CC_BASE_ADDRESS: - case I2CD_BASE_ADDRESS: + case APU_I2C0_BASE: + case APU_I2C1_BASE: + case APU_I2C2_BASE: + case APU_I2C3_BASE: dev->ops = &soc_amd_i2c_mmio_ops; break; } diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index a098775..6a6d776 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -7,10 +7,10 @@ #include "chip.h"
static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = { - { I2C_MASTER_MODE, I2CA_BASE_ADDRESS, "I2CA" }, - { I2C_MASTER_MODE, I2CB_BASE_ADDRESS, "I2CB" }, - { I2C_MASTER_MODE, I2CC_BASE_ADDRESS, "I2CC" }, - { I2C_MASTER_MODE, I2CD_BASE_ADDRESS, "I2CD" }, + { I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" }, + { I2C_MASTER_MODE, APU_I2C1_BASE, "I2CB" }, + { I2C_MASTER_MODE, APU_I2C2_BASE, "I2CC" }, + { I2C_MASTER_MODE, APU_I2C3_BASE, "I2CD" }, };
const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 3d01938..93e218d 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -11,10 +11,10 @@ #define ALINK_AHB_ADDRESS 0xfedc0000
/* I2C fixed address */ -#define I2CA_BASE_ADDRESS 0xfedc2000 -#define I2CB_BASE_ADDRESS 0xfedc3000 -#define I2CC_BASE_ADDRESS 0xfedc4000 -#define I2CD_BASE_ADDRESS 0xfedc5000 +#define APU_I2C0_BASE 0xfedc2000 +#define APU_I2C1_BASE 0xfedc3000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000
#if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000