[coreboot-gerrit] Change in coreboot[master]: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet p...

[Mike Banon (Code Review)]

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40495 )

Change subject: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches
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AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches

These scripts will help you to securely and conveniently apply five changes
CB:40484, CB:40485, CB:40490, CB:40488, CB:40489 to add the DDR3 XMP support.
Save to ./coreboot/ then run ./get_xmp_patches.sh , ./check... and ./apply...

Signed-off-by: Mike Banon 
Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d
---
A apply_xmp_patches.sh
A check_xmp_patches.sh
A get_xmp_patches.sh
A sha256sums_xmp_correct.txt
4 files changed, 85 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40495/1

diff --git a/apply_xmp_patches.sh b/apply_xmp_patches.sh
new file mode 100755
index 0000000..4320ee2
--- /dev/null
+++ b/apply_xmp_patches.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+###
+### https://review.coreboot.org/c/coreboot/+/40484
+### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128
+###
+patch -p1 < "./b8b7fb7.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40485
+### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable
+###
+patch -p1 < "./a81f3eb.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40490
+### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table
+###
+patch -p1 < "./bf4bd85.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40488
+### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
+###
+patch -p1 < "./3b9288e.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40489
+### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
+###
+patch -p1 < "./413db53.diff"
+###
diff --git a/check_xmp_patches.sh b/check_xmp_patches.sh
new file mode 100755
index 0000000..88a0375
--- /dev/null
+++ b/check_xmp_patches.sh
@@ -0,0 +1,16 @@
+#!/bin/sh
+rm -f "./sha256sums_xmp_my.txt"
+sha256sum "./b8b7fb7.diff" >  "./sha256sums_xmp_my.txt"
+sha256sum "./a81f3eb.diff" >> "./sha256sums_xmp_my.txt"
+sha256sum "./bf4bd85.diff" >> "./sha256sums_xmp_my.txt"
+sha256sum "./3b9288e.diff" >> "./sha256sums_xmp_my.txt"
+sha256sum "./413db53.diff" >> "./sha256sums_xmp_my.txt"
+if cmp -s "./sha256sums_xmp_my.txt" "./sha256sums_xmp_correct.txt"
+then
+    echo "SHA256 checksums are correct, please run ./apply_xmp_patches.sh"
+    exit 0
+else
+    echo "! MISMATCH ! See ./sha256sums_xmp_my.txt and ./sha256sums_xmp_correct.txt"
+    exit 1
+fi
+#
diff --git a/get_xmp_patches.sh b/get_xmp_patches.sh
new file mode 100755
index 0000000..34eba96
--- /dev/null
+++ b/get_xmp_patches.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+###
+### https://review.coreboot.org/c/coreboot/+/40484
+### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128
+###
+rm -f "./b8b7fb7.diff"
+wget "https://review.coreboot.org/changes/40484/revisions/1/patch?zip"
+unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b8b7fb7.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40485
+### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable
+###
+rm -f "./a81f3eb.diff"
+wget "https://review.coreboot.org/changes/40485/revisions/1/patch?zip"
+unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./a81f3eb.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40490
+### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table
+###
+rm -f "./bf4bd85.diff"
+wget "https://review.coreboot.org/changes/40490/revisions/1/patch?zip"
+unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./bf4bd85.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40488
+### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
+###
+rm -f "./3b9288e.diff"
+wget "https://review.coreboot.org/changes/40488/revisions/1/patch?zip"
+unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./3b9288e.diff"
+###
+### https://review.coreboot.org/c/coreboot/+/40489
+### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
+###
+rm -f "./413db53.diff"
+wget "https://review.coreboot.org/changes/40489/revisions/1/patch?zip"
+unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./413db53.diff"
+###
diff --git a/sha256sums_xmp_correct.txt b/sha256sums_xmp_correct.txt
new file mode 100644
index 0000000..e3ccb04
--- /dev/null
+++ b/sha256sums_xmp_correct.txt
@@ -0,0 +1,5 @@
+0b19e790c27cc4344f5427e2af62b3d8f5c729c49a528709689e4c1536e55daf  ./b8b7fb7.diff
+0f5816d40a56e5fe3201e539c2f6cae51a03ae606085731f3c70eb7f2a007bd5  ./a81f3eb.diff
+6749bbe5a8a33b0a32d214e32ffba4b6d7df740c73fd674c344653041e5103aa  ./bf4bd85.diff
+4579e9a7f3454e4909789b56d2fd6422129e31185a363cf6cd13485907b82b1d  ./3b9288e.diff
+d5161276160d1cf4d77a5252cb7f9855d2ff5de00dedea28790627d9a144b556  ./413db53.diff