Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48564 )
Change subject: [WIP] soc/amd/cezanne: add GPIO definitions ......................................................................
Patch Set 1:
(5 comments)
For the GPIO14x different between RN and CZN, I really doubt there is something wrong with the PPR.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 138: #define GPIO_22_IOMUX_EMMC_PWR_CTRL 1 #define GPIO_22_IOMUX_EMMC_PRW_CTRL 1 Is this PRW in Picasso folder a typo?
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 251: #define GPIO_140_IOMUX_GPIOxx 0 : #define GPIO_140_IOMUX_UART0_CTS_L 1 GPIO is func 1, and UART0_CTS_L is func 0, in RN PPR.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 255: #define GPIO_141_IOMUX_GPIOxx 0 : #define GPIO_141_IOMUX_UART0_RXD 1 For RN, same as 140.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 258: #define GPIO_142_IOMUX_GPIOxx 0 : #define GPIO_142_IOMUX_UART0_RTS_L 1 : #define GPIO_142_IOMUX_UART1_RXD 2 : #define GPIO_142_IOMUX_SD0_DATA0 3 For RN, For 142, GPIO is func 2. And func 0,1 are not right either.
https://review.coreboot.org/c/coreboot/+/48564/1/src/soc/amd/cezanne/include... PS1, Line 265: #define GPIO_144_IOMUX_GPIOxx 0 : #define GPIO_144_IOMUX_UART0_INTR 2 For RN, switch.