[coreboot-gerrit] [M] Change in coreboot[master]: soc/intel/cmn/tom: Cache TOM region early

[Arthur Heymans (Code Review)]

Attention is currently required from: Tarun Tuli, Jamie Ryu, Subrata Banik, Paul Menzel.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73272 )

Change subject: soc/intel/cmn/tom: Cache TOM region early
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Patch Set 10: Code-Review+2

(1 comment)

File src/soc/intel/common/basecode/tom/tom.c:

https://review.coreboot.org/c/coreboot/+/73272/comment/e779e2e8_0e0112c0 
PS9, Line 76: /* Update the TOM if required based on the input TOM address */
            : void update_tom(uint32_t addr)
            : {
            : 	struct tom_table tom;
            : 
            : 	/* Read and increment boot count */
            : 	if (tom_cmos_read(&tom) < 0) {
            : 		/* Structure invalid, re-initialize */
            : 		tom.signature = TOM_SIGNATURE;
            : 		tom.addr = 0;
            : 	}
            : 
            : 	/* Update TOM if required */
            : 	if (tom.addr == addr)
            : 		return;
            : 
            : 	tom.addr = addr;
            : 
            : 	/* Write the new count to CMOS */
            : 	tom_cmos_write(&tom);
            : 
            : 	printk(BIOS_DEBUG, "Updated the TOM address into CMOS 0x%x\n", tom.addr);
            : }
> > > How large is the performance impact from reading things from cmos? With this scheme it is read t […]

Ack