Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51674 )
Change subject: mb/amd/bilby: enable boot from NVMe SSD ......................................................................
mb/amd/bilby: enable boot from NVMe SSD
These changes involve NVMe specific GPIO programming to enable pcie NVMe SSD boot. Add nvme dev,func in devicetree and also remove unused GPIOs programmed in Bilby.
Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Signed-off-by: Ritul Guru ritul.bits@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/51674 Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/bilby/early_gpio.c M src/mainboard/amd/bilby/gpio.c M src/mainboard/amd/bilby/port_descriptors.c 4 files changed, 48 insertions(+), 55 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved ritul guru: Looks good to me, but someone else must approve
diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index addb328..c07415e 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -130,10 +130,10 @@ register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" - register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" register "gpp_clk_config[4]" = "GPP_CLK_REQ" - register "gpp_clk_config[5]" = "GPP_CLK_OFF" - register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_REQ" + register "gpp_clk_config[6]" = "GPP_CLK_REQ"
device cpu_cluster 0 on device lapic 0 on end @@ -143,7 +143,9 @@ device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge - device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 1.1 on end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 + device pci 1.5 on end # NVMe device pci 8.0 on end # Dummy Host Bridge device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU diff --git a/src/mainboard/amd/bilby/early_gpio.c b/src/mainboard/amd/bilby/early_gpio.c index b6ca995..0a9d266 100644 --- a/src/mainboard/amd/bilby/early_gpio.c +++ b/src/mainboard/amd/bilby/early_gpio.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include <soc/gpio.h> #include "gpio.h"
/* GPIO pins used by coreboot should be initialized in bootblock */
static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* assert PCIe reset */ + PAD_GPO(GPIO_6, HIGH), /* not LLB */ PAD_GPI(GPIO_12, PULL_UP), /* not USB_OC1_L */ @@ -14,14 +15,16 @@ PAD_GPI(GPIO_18, PULL_UP), /* SDIO eMMC power control */ PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE), - /* PCIe Reset 0 */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* PCIe Reset 1 */ - PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* PCIe Reset to DP0, DP1, J2105, TP, FP */ + PAD_GPO(GPIO_27, HIGH), /* eSPI CS# */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* GPP_10G_SELECT => High=10G, Low=x2 NVME (work with AGPIO89) */ + PAD_GPO(GPIO_42, LOW), /* FANOUT0 */ PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* APU_COMBO_GPP_SW => High=SATA, Low=x2 NVME (work with EGPIO42) */ + PAD_GPO(GPIO_89, LOW), /* PC beep to codec */ PAD_NF(GPIO_91, SPKR, PULL_NONE), }; diff --git a/src/mainboard/amd/bilby/gpio.c b/src/mainboard/amd/bilby/gpio.c index 999672e..0d49816 100644 --- a/src/mainboard/amd/bilby/gpio.c +++ b/src/mainboard/amd/bilby/gpio.c @@ -9,8 +9,6 @@ * ramstage. */ static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* EC SCI# */ - PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), /* I2S SDIN */ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), /* I2S LRCLK */ @@ -23,8 +21,6 @@ PAD_GPI(GPIO_31, PULL_UP), /* NFC IRQ */ PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), - /* NFC wake output# */ - PAD_GPO(GPIO_89, HIGH), };
void mainboard_program_gpios(void) diff --git a/src/mainboard/amd/bilby/port_descriptors.c b/src/mainboard/amd/bilby/port_descriptors.c index 8fc94f8..2801c73 100644 --- a/src/mainboard/amd/bilby/port_descriptors.c +++ b/src/mainboard/amd/bilby/port_descriptors.c @@ -3,51 +3,25 @@ #include <soc/platform_descriptors.h> #include <types.h>
-static const fsp_dxio_descriptor pollock_dxio_descriptors[] = { - { /* NVME SSD */ +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { + { /* MXM - Entry 0 */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0 - }, - { /* WWAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 1, - .function_number = 4, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2 - }, - { /* LAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 4, - .end_logical_lane = 4, + .start_logical_lane = 15, + .end_logical_lane = 8, .device_number = 1, .function_number = 1, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1 + .clk_req = CLK_REQ3 }, - { /* WLAN */ + { /* DEVICE_ID_DT - Entry 1 */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_logical_lane = 5, - .end_logical_lane = 5, + .start_logical_lane = 4, + .end_logical_lane = 7, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -55,12 +29,25 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ4 - } + }, + { /* PCIE M.2 x2 - Entry 2 */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 3, + .device_number = 1, + .function_number = 5, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, };
-fsp_ddi_descriptor pollock_ddi_descriptors[] = { - { /* DDI0 - eDP */ - .connector_type = EDP, +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DP, .aux_index = AUX1, .hdp_index = HDP1 }, @@ -71,6 +58,11 @@ }, { /* DDI2 - DP */ .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { /* DDI3 - DP */ + .connector_type = DP, .aux_index = AUX4, .hdp_index = HDP4, } @@ -80,8 +72,8 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *dxio_descs = pollock_dxio_descriptors; - *dxio_num = ARRAY_SIZE(pollock_dxio_descriptors); - *ddi_descs = pollock_ddi_descriptors; - *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); + *dxio_descs = pco_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pco_dxio_descriptors); + *ddi_descs = pco_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); }