Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46260 )
Change subject: soc/intel/common: Add PCIe Runtime D3 driver for ACPI ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46260/10/src/soc/intel/common/block... File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/46260/10/src/soc/intel/common/block... PS10, Line 11: unsigned int clock_pin; /* SRCCLK assigned to this root port */
This is available in the SoC chip info, means one less place to forget something 😊
The problem I ran into is that the soc chip info headers are soc-specific (and not all implement the same srcclk option) and this is meant to be common code.
It might be nice if we had a common chip header for some things like PCI configuration which could be inherited by all the SOCs..