Deomid "rojer" Ryabkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51230 )
Change subject: soc/intel/xeon_sp: Set the MRC "cold boot required" status bit ......................................................................
soc/intel/xeon_sp: Set the MRC "cold boot required" status bit
If bit 0 of byte 0x47 is set FSP will perform full memory training even if previously saved data is supplied.
Up to and including FSP 2021 WW01 it was reset internally at the end of PostMemoryInit. Starting with WW03 this is no longer the case and Intel advised that this bit should be reset externally if valid MRC data is present.
Change-Id: I9c4191d2fa2e0203b3464dcf40d845ede5f14c6b Signed-off-by: Deomid "rojer" Ryabkov rojer9@fb.com --- M 3rdparty/blobs M 3rdparty/chromeec M 3rdparty/fsp M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/cpx/romstage.c 5 files changed, 21 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/51230/1
diff --git a/3rdparty/blobs b/3rdparty/blobs index 02ab6c6..aadb2e5 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 02ab6c66480ccd5f6bdfddd6fa090156d436fa4b +Subproject commit aadb2e5f9bfb53f0fa3493a4d018550486cc5e59 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index a2390f3..a1afae4 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit a2390f3c505a4684535c08da27736099a63850fe +Subproject commit a1afae4e002a3eccd7835ac898259b0690e9e61a diff --git a/3rdparty/fsp b/3rdparty/fsp index e7138bf..2e4f1d3 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit e7138bf11508b8b82350bd17fb611b67c0c64e6b +Subproject commit 2e4f1d3e85584a233fac79ad3e7d2e4975097932 diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 1311678..2a5ef58 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -103,4 +103,7 @@
typedef struct soc_intel_xeon_sp_cpx_config config_t;
+/* Address of the MRC status byte in CMOS. */ +#define CMOS_MRC_STATUS_ADDR 0x47 + #endif diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index c1cb0ca..9ca960e 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -8,10 +8,12 @@ #include <fsp/util.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <pc80/mc146818rtc.h> #include <soc/ddr.h> #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> +#include <stdbool.h> #include <string.h>
#include "chip.h" @@ -124,6 +126,16 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); }
+static void set_cmos_mrc_cold_boot_flag(bool cold_boot_required) +{ + uint8_t mrc_status = cmos_read(CMOS_MRC_STATUS_ADDR); + uint8_t new_mrc_status = (mrc_status & 0xfe) | ((uint8_t) cold_boot_required); + printk(BIOS_SPEW, "MRC status: 0x%02x want 0x%02x\n", mrc_status, new_mrc_status); + if (new_mrc_status != mrc_status) { + cmos_write(new_mrc_status, CMOS_MRC_STATUS_ADDR); + } +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; @@ -190,4 +202,7 @@ m_cfg->isocEn = 0;
mainboard_memory_init_params(mupd); + + bool cold_boot_required = (mupd->FspmArchUpd.NvsBufferPtr == 0); + set_cmos_mrc_cold_boot_flag(cold_boot_required); }