[coreboot-gerrit] [L] Change in coreboot[main]: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81219?usp=email )

Change subject: soc/intel/xeon_sp: Share DDR codes acorss Xeon-SP platforms
......................................................................

Patch Set 12:

(1 comment)

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/81219/comment/248f6690_2b2c75aa :
PS12, Line 336: {
> not sure if we can share this or not.

save_dimm_info share cannot be made since there are trivial difference across SoCs, maybe some later work could try to merge some common logics, but we can do that in separate patches.