Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45723 )
Change subject: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL in s0ix conditional ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45723/2/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/45723/2/src/soc/intel/cannonlake/ch... PS2, Line 61: uint8_t s0ix_allow_xtal_on;
I'm afraid I don't follow. Intel documents both the XTAL shutdown and the SLP_S0# assertion (what is what we want to achieve with S0ix, AIUI) as effects of low-power state 3 (LP3). Not as requirements of one another.
This is my understanding: On C10 entry, PMC checks clock requests for XTAL to determine whether it is okay to enter S0i3 (LP3) i.e. XTAL is one of the qualification factors for S0i3 entry. However, it can be ignored by setting the XTAL disqualification bit. Thus, even if XTAL remains enabled on C10 entry, PMC ignores its state when making the determination for S0i3 entry.
Where is their relation documented? IIRC, we can't have S0ix with that timer anyway.
I never found actual documentation on this. Mostly during discussions with Intel. There was a patch series at one point that Intel had: https://review.coreboot.org/c/coreboot/+/22299 which basically indicated that: 8254 clock gating is required for XTAL shutdown XTAL shutdown is necessary for S0ix unless disqualification bit is set.