Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34603 )
Change subject: mb/asus: Add ASUS H110M-E/M.2 mainboard ......................................................................
Patch Set 69:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 17: subdirs-y += spd
what's that?
Garbage!
(it is only necessary when using memory-down)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 252: device pci 00.0 on end # Host Bridge : device pci 01.0 on end # PEG : device pci 02.0 on end # Integrated Graphics Device : device pci 14.0 on end # USB xHCI : device pci 14.1 off end # USB xDCI (OTG) : device pci 14.2 on end # Thermal Subsystem : device pci 15.0 off end # I2C #0 : device pci 15.1 off end # I2C #1 : device pci 15.2 off end # I2C #2 : device pci 15.3 off end # I2C #3 : device pci 16.0 on end # Management Engine Interface 1 : device pci 16.1 off end # Management Engine Interface 2 : device pci 16.2 off end # Management Engine IDE-R : device pci 16.3 off end # Management Engine KT Redirection : device pci 16.4 off end # Management Engine Interface 3 : device pci 17.0 on end # SATA : device pci 19.0 off end # UART #2 : device pci 19.1 off end # I2C #5 : device pci 19.2 off end # I2C #4 : device pci 1c.0 on end # PCI Express Port 1 : device pci 1c.1 off end # PCI Express Port 2 : device pci 1c.2 off end # PCI Express Port 3 : device pci 1c.3 off end # PCI Express Port 4 : device pci 1c.4 on end # PCI Express Port 5 : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 on end # PCI Express Port 8 : device pci 1d.0 on end # PCI Express Port 9 : device pci 1d.1 off end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 : device pci 1e.0 off end # UART #0 : device pci 1e.1 off end # UART #1 : device pci 1e.2 off end # GSPI #0 : device pci 1e.3 off end # GSPI #1 : device pci 1e.4 off end # eMMC : device pci 1e.5 off end # SDIO : device pci 1e.6 off end # SDCard : device pci 1f.0 on # LPC bridge
tabs are your friend :)
What he means: Use tabs to align these things.
device pci 14.2 on end <TAB HERE> # Thermal Subsystem device pci 15.0 off end <TAB HERE> # I2C #0
Note that there are two spaces after an `on` keyword: that way, the `end` keywords are aligned 😄
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 305: evice pnp 2e.6 off end # CIR : device pnp 2e.7 off end # GPIO7 : device pnp 2e.107 off end # GPIO8 : device pnp 2e.8 off end # WDT : device pnp 2e.108 off end # GPIO0 : device pnp 2e.308 off end # GPIO base : device pnp 2e.408 off end # WDTMEM : device pnp 2e.9 off end # GPIO2 : device pnp 2e.109 off end # GPIO3 : device pnp 2e.209 off end # GPIO4 : device pnp 2e.309 off end # GPIO5 : device pnp 2e.a on end # ACPI : device pnp 2e.b off # HWM, LED
nit: this could be formatted to enhance readability like the ones from 322 😊
(clarification: `322` refers to the line number of this file.)
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... File src/mainboard/asus/h110m-e_m2/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/34603/69/src/mainboard/asus/h110m-e... PS69, Line 161: 0x04000100
this will trigger an error "gpio_pad_reset_config_override: Logical […]
Good catch: the log is spammed with those. Can't we use proper macros instead?