[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts

[Harsha B R (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P.

Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69741 )

Change subject: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
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Patch Set 11:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69741/comment/c00bb8f5_9e8a821d 
PS10, Line 13: FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage
> Note: building the MTLRVP can't be a test statement, the purpose of the test is to ensure the code t […]

Ack

File src/mainboard/intel/mtlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/69741/comment/38c720c1_59fffe31 
PS10, Line 23: 	spd_index = 1;
> https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/adlrvp/.... […]

Many Thanks!