Attention is currently required from: Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Michal Motyl, Tim Chu. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62064 )
Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ......................................................................
soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances.
TEST=Able to build brya.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 --- M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/finalize.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c 24 files changed, 47 insertions(+), 173 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62064/1
diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h index b65b24d..98843d1 100644 --- a/src/soc/intel/alderlake/include/soc/pm.h +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -162,9 +162,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index d8308b4..f8b858f 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -133,20 +133,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 3c0b1e7..1e6a927 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -242,7 +242,4 @@ /* STM Support */ uint16_t get_pmbase(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 79ece4b..fbb2345 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -237,17 +237,3 @@ reg32 |= SLEEP_AFTER_POWER_FAIL; write32p(gen_pmcon1, reg32); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON1); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON1), reg_val); -} diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 59b2ba0..d345e07 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void);
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index a79d262..38a0ce7 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -127,20 +127,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index bb38204..fc65a08 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -178,6 +178,9 @@ */ void pmc_gpe_init(void);
+/* Clear PMC GEN_PMCON_A register status bits */ +void pmc_clear_pmcon_sts(void); + /* Power Management Utility Functions. */
/* Returns PMC base address */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index da78d5c..9eb8680 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -5,6 +5,7 @@ #include <assert.h> #include <bootmode.h> #include <device/mmio.h> +#include <device/pci.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <console/console.h> @@ -14,6 +15,7 @@ #include <intelblocks/tco.h> #include <option.h> #include <security/vboot/vboot_common.h> +#include <soc/pci_devs.h> #include <soc/pm.h> #include <stdint.h> #include <string.h> @@ -580,6 +582,44 @@ gpio_route_gpe(dw0, dw1, dw2); }
+#if ENV_RAMSTAGE +static void pmc_clear_pmcon_sts_using_mmio(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + +static void pmc_clear_pmcon_sts_using_pci_cfg(void) +{ + uint32_t reg_val; + struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + + reg_val = pci_read_config32(dev, GEN_PMCON_A); + reg_val &= ~(MS4V); + + pci_write_config32(dev, GEN_PMCON_A, reg_val); +} + +/* + * Clear PMC GEN_PMCON_A register status bits: + * SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit + */ +void pmc_clear_pmcon_sts(void) +{ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE)) + pmc_clear_pmcon_sts_using_pci_cfg(); + else + pmc_clear_pmcon_sts_using_mmio(); +} +#endif + void pmc_set_power_failure_state(const bool target_on) { const unsigned int state = get_uint_option("power_on_after_fail", diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 4c0c998..194067a 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -37,6 +37,7 @@ select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SMBUS select SUPPORT_CPU_UCODE_IN_CBFS select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 2dc40a5..6fc9d90 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -45,7 +45,4 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 822e50e..92e5694 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -235,18 +235,3 @@ uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
void clear_pmc_status(void) { /* TODO */ } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -} diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 6ebbbfa..6a86787 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 9bd431d..0109215 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index ad2beff..05db830 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void);
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index f552a8c..b7829b2 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index 11d6663..eea875b 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -155,9 +155,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index d9ecb63..fb1aecd 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -126,20 +126,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 51be0eb..f0ce146 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -189,7 +189,4 @@ /* STM Support */ uint16_t get_pmbase(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index ded44dc..fe26ebf 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -265,18 +265,3 @@ reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(dev, GEN_PMCON_B, reg8); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -} diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index d62e8ad..cb0781a 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -162,9 +162,6 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index aee2b3b..e854385 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -132,20 +132,6 @@ write8(addr, disb_val); }
-void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index 76e3ef1..7e7cfa2 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -5,6 +5,7 @@ #include <console/debug.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -43,6 +44,8 @@ apm_control(APM_CNT_FINALIZE); lock_pam0123();
+ pmc_clear_pmcon_sts(); + post_code(POST_OS_BOOT); }
diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index 63b15cd..b4d6df9 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -121,7 +121,4 @@
void pmc_lock_smi(void);
-/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - #endif diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index 14c7da8..c63285c 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -179,18 +179,3 @@ reg8 |= SLEEP_AFTER_POWER_FAIL; pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); } - -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - const pci_devfn_t dev = PCH_DEV_PMC; - - reg_val = pci_read_config32(dev, GEN_PMCON_A); - /* - * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit - */ - reg_val &= ~(MS4V); - - pci_write_config32(dev, GEN_PMCON_A, reg_val); -}