Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34522
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix ......................................................................
soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ix
Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state.
BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE.
Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/finalize.c 2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34522/2