Attention is currently required from: Felix Singer, Tarun Tuli, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73133 )
Change subject: soc/intel/cmn/block/cse: ME source code at common location ......................................................................
Patch Set 5:
(3 comments)
File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/73133/comment/0b9cd4d2_22f755cd PS5, Line 8: ifeq ($(CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT),y) : ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse_me.c : endif after u address https://review.coreboot.org/c/coreboot/+/73128/comments/ff9fa8c4_adfad1b3,yo... can rewrite this as
ramstage-$(CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT) += cse_me.c
btw, what is this name `cse_me.c`?
File src/soc/intel/common/block/cse/cse_me.c:
https://review.coreboot.org/c/coreboot/+/73133/comment/5ba9bb38_99cc4b19 PS5, Line 2: why don't u move this into cse.c file ?
https://review.coreboot.org/c/coreboot/+/73133/comment/407ed59c_e7131ce0 PS5, Line 11: /* : * ME manufacturing mode is disabled if the descriptor is locked and fuses : * are programmed. Additionally, if the SoC supports manufacturing variable, should be locked. : */ u can drop this