Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43607 )
Change subject: soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU ......................................................................
soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU
Set power limits in devicetree for Tiger Lake Y-SKU based volteer variant boards.
BUG=b:152639350 BRANCH=None TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc Signed-off-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Caveh Jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/systemagent.c 3 files changed, 25 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e0d3bea..0e8ad3e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -211,15 +211,25 @@ # Enable DPTF register "dptf_enable" = "1"
+ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, + }" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 60, .tdp_pl4 = 105, }" - register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 38, - .tdp_pl4 = 71, + register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 66, + }" + register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 40, + .tdp_pl4 = 83, }"
register "Device4Enable" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 59dab58..3d910ce 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -23,9 +23,11 @@ #define MAX_HD_AUDIO_SSP_LINKS 6
/* The first two are for TGL-U */ -#define POWER_LIMITS_U_4_CORE 0 -#define POWER_LIMITS_U_2_CORE 1 -#define POWER_LIMITS_MAX 2 +#define POWER_LIMITS_U_2_CORE 0 +#define POWER_LIMITS_U_4_CORE 1 +#define POWER_LIMITS_Y_2_CORE 2 +#define POWER_LIMITS_Y_4_CORE 3 +#define POWER_LIMITS_MAX 4
/* * Enable External V1P05 Rail in: BIT0:S0i1/S0i2, diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index fd611bb..29487a8 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -84,6 +84,12 @@ case PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2: soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE]; break; + case PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2: + soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE]; + break; + case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2: + soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE]; + break; default: printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits " "configuration\n", sa_pci_id);