Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49893 )
Change subject: xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices ......................................................................
xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices
The values can be used during SMBIOS type 16 creation.
Tested=On OCP Delta Lake, dmidecode -t 16 to verify. Handle 0x000A, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Single-bit ECC Maximum Capacity: 1146 GB Error Information Handle: Not Provided Number Of Devices: 6
Change-Id: Id8f92dc96a7a3eb2e6db330adda98a7fe6d516c8 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/49893 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/xeon_sp/cpx/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index e423d0a..6025f2a 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -60,6 +60,9 @@ return; } memset(mem_info, 0, sizeof(*mem_info)); + /* According to Dear Customer Letter it's 1.12 TB per processor. */ + mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET; + mem_info->number_of_devices = CONFIG_DIMM_MAX; dimm_max = ARRAY_SIZE(mem_info->dimm); vdd_voltage = get_ddr_voltage(hob->DdrVoltage); /* For now only implement for one socket and hard-coded for DDR4 */