Robbie Zhang (robbie.zhang@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18366
-gerrit
commit 87d6fa08af73d2b9c5cf940b2baba4896d62362c Author: Robbie Zhang robbie.zhang@intel.com Date: Tue Feb 14 15:12:17 2017 -0800
intel/skylake: add function is_secondary_thread()
There are MSRs that are programmable per-core not per-thread, so add a function to check whether current executing CPU is a primary core or a "hyperthreaded"/secondary core. For instance when trying to program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary thread avoiding exeception.
Change-Id: Ic9648351fadf912164a39206788859baf3e5c173 Signed-off-by: Robbie Zhang robbie.zhang@intel.com --- src/soc/intel/skylake/cpu.c | 11 +++++++++++ src/soc/intel/skylake/include/soc/cpu.h | 1 + 2 files changed, 12 insertions(+)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index fd726c8..4784889 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -431,6 +431,17 @@ static int adjust_apic_id(int index, int apic_id) return index; }
+/* Check whether the current CPU is the sibling hyperthread. */ +int is_secondary_thread(void) +{ + int apic_id; + apic_id = lapicid(); + + if (!ht_disabled && (apic_id & 1)) + return 1; + return 0; +} + static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index ecb9833..bf720e6 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -63,5 +63,6 @@ int cpu_config_tdp_levels(void); u32 cpu_family_model(void); u32 cpu_stepping(void); int cpu_is_ult(void); +int is_secondary_thread(void);
#endif