[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP]

[Maxim Polyakov (Code Review)]

Hello build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39425

to look at the new patch set (#5).

Change subject: soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP]
......................................................................

soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver [WIP]

Adds definitions that allow to use the common GPIO driver to configure
the Lewisburg PCH pads. Using the GPIO configuration from common/gpio,
unlike the FSP-style definitions from Intel RefCode [1] definitions,
is more understandable and makes the motherboards code much cleaner. In
addition, we can use utilities, such as intetool, to analyze the
configuration of proprietary firmware to add support for new server
motherboards with Skylake-SP processors.

The pin layout in this patch corresponds to the driver in the Linux
kernel for Lewisburg PCH GPIO hardware [2]

[1] https://designintools.intel.com/product_p/stlgrn45.htm
[2] drivers/pinctrl/intel/pinctrl-lewisburg.c

These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/acpi/gpio.asl
A src/soc/intel/xeon_sp/gpio.c
A src/soc/intel/xeon_sp/include/soc/gpio.h
A src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
6 files changed, 1,108 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39425/5