Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
Sorry, the latter part again is untrue. I was and I am able to change them in coreboot, just like the "normal" GPIOs. I've been experimenting with those "special" GPIOs a few days on CML.
All GPIOs are MMIO mapped hence you can do experiment as long as you know the addresses.
FSP indirectly claims being part of "BIOS" in multiple comments in the source. You see comments like "BIOS is expected to do xyz", at code locations doing exactly what's in the comments. Yes, that may be a weak conclusion. However, the point is it does program these GPIOs.
FSP meant to do SoC GPIO programming in NF, no doubt about that but as per guideline i have received from GPIO owner, your interest point GPIOs are not going to program in FSP as well hence SOC default we are going to use.
I forgot this one:
Proving little more information here all GPIO PIN that Michael has asked like Azalia, CPU, VGPIO are part of GPIO COMM 3 which we don't expose for Linux driver and BIOS. i hope this is good to have information.
We may not want to expose it to Linux but Linux (OS) != coreboot (BIOS). Claiming not exposing it to BIOS sounds a bit dishonest, given the fact that they are indeed exposed to FSP which is part of BIOS.
So far i don't see such programming in FSP and as i said the plan is to use SoC default. Also this is what i'm suppose to upstream at this moment, i have clear legal and all other doubts based on board schematics that those GPIO we might not need to touch in coreboot as well.