[coreboot-gerrit] Change in coreboot[master]: src/northbridge: Use SPDX for GPL-2.0-only files

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40056

to look at the new patch set (#3).

Change subject: src/northbridge: Use SPDX for GPL-2.0-only files
......................................................................

src/northbridge: Use SPDX for GPL-2.0-only files

Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad
Signed-off-by: Angel Pons 
---
M src/northbridge/amd/agesa/BiosCallOuts.h
M src/northbridge/amd/agesa/agesa_helper.h
M src/northbridge/amd/agesa/dimmSpd.h
M src/northbridge/amd/agesa/family14/acpi/northbridge.asl
M src/northbridge/amd/agesa/family14/chip.h
M src/northbridge/amd/agesa/family14/dimmSpd.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family14/pci_devs.h
M src/northbridge/amd/agesa/family14/state_machine.c
M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl
M src/northbridge/amd/agesa/family15tn/chip.h
M src/northbridge/amd/agesa/family15tn/dimmSpd.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family15tn/pci_devs.h
M src/northbridge/amd/agesa/family15tn/state_machine.c
M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl
M src/northbridge/amd/agesa/family16kb/chip.h
M src/northbridge/amd/agesa/family16kb/dimmSpd.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/agesa/family16kb/pci_devs.h
M src/northbridge/amd/agesa/family16kb/state_machine.c
M src/northbridge/amd/agesa/nb_common.h
M src/northbridge/amd/agesa/state_machine.h
M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl
M src/northbridge/amd/pi/00630F01/chip.h
M src/northbridge/amd/pi/00630F01/dimmSpd.c
M src/northbridge/amd/pi/00630F01/iommu.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00630F01/pci_devs.h
M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
M src/northbridge/amd/pi/00660F01/chip.h
M src/northbridge/amd/pi/00660F01/dimmSpd.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
M src/northbridge/amd/pi/00730F01/chip.h
M src/northbridge/amd/pi/00730F01/dimmSpd.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/00730F01/pci_devs.h
M src/northbridge/amd/pi/00730F01/state_machine.c
M src/northbridge/amd/pi/dimmSpd.h
M src/northbridge/amd/pi/nb_common.h
M src/northbridge/intel/e7505/memmap.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/e7505/raminit.h
M src/northbridge/intel/e7505/romstage.c
M src/northbridge/intel/gm45/acpi.c
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/gm45/acpi/hostbridge.asl
M src/northbridge/intel/gm45/acpi/peg.asl
M src/northbridge/intel/gm45/bootblock.c
M src/northbridge/intel/gm45/chip.h
M src/northbridge/intel/gm45/early_init.c
M src/northbridge/intel/gm45/early_reset.c
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/gm45/igd.c
M src/northbridge/intel/gm45/iommu.c
M src/northbridge/intel/gm45/memmap.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/pcie.c
M src/northbridge/intel/gm45/pm.c
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/gm45/raminit_rcomp_calibration.c
M src/northbridge/intel/gm45/raminit_read_write_training.c
M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
M src/northbridge/intel/gm45/romstage.c
M src/northbridge/intel/gm45/thermal.c
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/haswell/acpi/peg.asl
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/chip.h
M src/northbridge/intel/haswell/early_init.c
M src/northbridge/intel/haswell/finalize.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/haswell/mchbar_regs.h
M src/northbridge/intel/haswell/memmap.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/haswell/raminit.h
M src/northbridge/intel/haswell/report_platform.c
M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
M src/northbridge/intel/i440bx/debug.c
M src/northbridge/intel/i440bx/memmap.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/acpi.c
M src/northbridge/intel/i945/acpi/hostbridge.asl
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/i945/acpi/igd.asl
M src/northbridge/intel/i945/acpi/peg.asl
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/i945/chip.h
M src/northbridge/intel/i945/debug.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/errata.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/memmap.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/i945/rcven.c
M src/northbridge/intel/i945/romstage.c
M src/northbridge/intel/ironlake/acpi.c
M src/northbridge/intel/ironlake/acpi/hostbridge.asl
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/ironlake/bootblock.c
M src/northbridge/intel/ironlake/chip.h
M src/northbridge/intel/ironlake/early_init.c
M src/northbridge/intel/ironlake/finalize.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/ironlake.h
M src/northbridge/intel/ironlake/memmap.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/ironlake/raminit.h
M src/northbridge/intel/ironlake/romstage.c
M src/northbridge/intel/ironlake/smi.c
M src/northbridge/intel/pineview/acpi.c
M src/northbridge/intel/pineview/acpi/hostbridge.asl
M src/northbridge/intel/pineview/acpi/peg.asl
M src/northbridge/intel/pineview/acpi/pineview.asl
M src/northbridge/intel/pineview/bootblock.c
M src/northbridge/intel/pineview/chip.h
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/pineview/mchbar_regs.h
M src/northbridge/intel/pineview/memmap.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/x4x/acpi.c
M src/northbridge/intel/x4x/acpi/hostbridge.asl
M src/northbridge/intel/x4x/acpi/peg.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/gma.c
M src/northbridge/intel/x4x/memmap.c
M src/northbridge/intel/x4x/northbridge.c
M src/northbridge/intel/x4x/x4x.h
144 files changed, 288 insertions(+), 1,896 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/40056/3