[coreboot-gerrit] Change in ...coreboot[master]: nb/x4x: Rename {ddr,fsb}2mhz as {ddr,fsb}_to_mhz

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33491

Change subject: nb/x4x: Rename {ddr,fsb}2mhz as {ddr,fsb}_to_mhz
......................................................................

nb/x4x: Rename {ddr,fsb}2mhz as {ddr,fsb}_to_mhz

Change-Id: I0442cc5bc54efd7e2c4e5496182c8df85acbcf91
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/intel/x4x/x4x.h
3 files changed, 8 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/33491/1

diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index bd6536a..8013af9 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -461,9 +461,9 @@
 {
    printk(BIOS_DEBUG, "Selected timings:\n");
    printk(BIOS_DEBUG, "\tFSB:  %dMHz\n",
-		fsb2mhz(s->selected_timings.fsb_clk));
+		fsb_to_mhz(s->selected_timings.fsb_clk));
    printk(BIOS_DEBUG, "\tDDR:  %dMHz\n",
-		ddr2mhz(s->selected_timings.mem_clk));
+		ddr_to_mhz(s->selected_timings.mem_clk));

printk(BIOS_DEBUG, "\tCAS:  %d\n", s->selected_timings.CAS);
    printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS);
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 422b0ff..42fb554 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -32,12 +32,12 @@

#define ME_UMA_SIZEMB 0

-u32 fsb2mhz(u32 speed)
+u32 fsb_to_mhz(u32 speed)
 {
    return (speed * 267) + 800;
 }

-u32 ddr2mhz(u32 speed)
+u32 ddr_to_mhz(u32 speed)
 {
    static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 };

@@ -578,8 +578,8 @@
    	reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr);
    	reg32 = (u32)((reg32 / fsb) << 8);
    	reg32 |= 0x0e000000;
-		if ((fsb2mhz(s->selected_timings.fsb_clk) /
-		     ddr2mhz(s->selected_timings.mem_clk)) > 2) {
+		if ((fsb_to_mhz(s->selected_timings.fsb_clk) /
+		     ddr_to_mhz(s->selected_timings.mem_clk)) > 2) {
    		reg32 |= 1 << 24;
    	}
    	MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32);
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index a7efb17..5772336 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -378,8 +378,8 @@
 void sdram_initialize(int boot_path, const u8 *spd_map);
 void do_raminit(struct sysinfo *, int fast_boot);
 void rcven(struct sysinfo *s);
-u32 fsb2mhz(u32 speed);
-u32 ddr2mhz(u32 speed);
+u32 fsb_to_mhz(u32 speed);
+u32 ddr_to_mhz(u32 speed);
 u32 test_address(int channel, int rank);
 void dqsset(u8 ch, u8 lane, const struct dll_setting *setting);
 void dqset(u8 ch, u8 lane, const struct dll_setting *setting);