[coreboot-gerrit] Change in coreboot[master]: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 de...

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33131 )

Change subject: mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C
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mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree C

PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Sarien.

Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4
Signed-off-by: Sumeet Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 739a849..d3aab62 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -163,6 +163,9 @@

register "tcc_offset" = "10"

+	# PCH Thermal Trip Temperature in deg C
+	register "common_soc_config.pch_thermal_trip" = "77"
+
    register "common_soc_config" = "{
    	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
    	.i2c[0] = {