Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... PS9, Line 167: /* Cache the ROM as WP just below 4GiB. */
You do not setup TSEG cache here in the original code? That's where your ramstage will be copied before the jump, see run_ramstage(). Unless you have NO_STAGE_CACHE=y in your config.
You are correct, we should have also cache TSEG region for that matter. This will give some more savings for sure
Maybe I missed something? That would totally have messed up any performance numbers you have gathered so far.
performance numbers are coming "not from stage_cache" (for now what I'm measuring) rather between (top_of_ram - 16MB) till top_of_ram, in this area we have entire operation going on.
For an example: I'm working on CML hatch.
postcar gets loaded into 0x99c20000 size 0x4598 ramstage gets loaded into 0x99bcb000 size 0x5ddd8\
[all above ranges are between between (top_of_ram - 16MB) till top_of_ram, top_of_ram = 0x9a000000 and TSEG is between 0x9a000000 till 0x9ac00000]
in case of S3 resume, yes, it won't load from cbfs rather it will pick from stage_cache, there we should get savings and we should also try to make TSEG area also into WB cache if possible.