[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports
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Patch Set 8:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@10 
PS8, Line 10: and jsl in fsp params.
> We do not have any mainboards added for PCH-H as of now. […]

Ack.

Though, it shows that your approach creates more work in case somebody
wants to add those in the future.

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... 
PS8, Line 108: 	for (i = 0; i < CONFIG_SOC_INTEL_USB2_PORT_MAX; i++) {
> Hello Nico. […]

Writing more error-prone code (people have to maintain the correct numbers in
Kconfig, make sure they agree with external header files and that an external
program (FSP) does it's job well even if not all of its inputs are set to a
defined state), is not worth saving 6 loop iterations, imho.