[coreboot-gerrit] Change in coreboot[master]: mb/{i945}: Remove 2nd write to RCBA32(V0CTL)

[HAOUAS Elyes (Code Review)]

Hello Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph, Arthur Heymans, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32915

to look at the new patch set (#6).

Change subject: mb/{i945}: Remove 2nd write to RCBA32(V0CTL)
......................................................................

mb/{i945}: Remove 2nd write to RCBA32(V0CTL)

The write on this register is already done here: 'i945/early_init.c'

Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3
Signed-off-by: Elyes HAOUAS 
---
M src/mainboard/apple/macbook21/romstage.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/lenovo/t60/romstage.c
5 files changed, 0 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/6