Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39769 )
Change subject: nb/intel/haswell: Implement proper backlight PWM config ......................................................................
nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy variants was overridden with 200Hz like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 8 files changed, 44 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39769/1
diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index f2a9520..2d07683 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index 8951e99..4cf1e72 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index 6451d95..7bb18c0 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 2cad23b..159d51a 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -12,9 +12,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 1022e77..621159a 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -12,7 +12,7 @@ register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" - register "gpu_pch_backlight" = "0x12ba12ba" + register "gpu_pch_backlight_pwm_hz" = "220" device cpu_cluster 0x0 on chip cpu/intel/haswell register "c1_acpower" = "1" diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 06ce371..5e631cf 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -107,7 +107,4 @@ depends on VBOOT default "mrc.bin"
-config INTEL_GMA_BCLV_OFFSET - default 0x48254 - endif diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index cfc2884..d7ef27d 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -36,8 +36,11 @@ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
- u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ - u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity;
bool gpu_ddi_e_connected;
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index eed6740..873c7ea 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -347,14 +347,36 @@ gtt_write(PCH_PP_DIVISOR, reg32); }
- /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* Enforce the PCH PWM function, as so does Linux. + The CPU PWM controls are disabled after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* Reference clock is either 24MHz or 135MHz. We can choose + either a 16 or a 128 step increment. Use 16 if we would + have less than 100 steps otherwise. */ + const unsigned int refclock = CONFIG(INTEL_LYNXPOINT_LP) + ? 24 * 1000 * 1000 + : 135 * 1000 * 1000; + const unsigned int hz_limit = refclock / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 |= 1 << 5; + } else { + pwm_increment = 128; + south_chicken2 &= ~(1 << 5); + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); }
/* Get display,pipeline,and DDI registers into a basic sane state */