[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, TangYiwei, Tim Chu.

Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81316?usp=email

to look at the new patch set (#22).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes
......................................................................

soc/intel/xeon_sp: Add GraniteRapids initial codes

coreboot GNR (GraniteRapids) is a FSP2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (SierraForest) SoC.

This patch initially setups the code set. All register definitions
are forked from SPR (SapphireRapids) and EBG (Emmisburg PCH)'s
codes are reused.

Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu 
Signed-off-by: Gang Chen 
Signed-off-by: Jincheng Li 
---
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_gen1.c
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/acpi/platform.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/uncore.c
24 files changed, 1,327 insertions(+), 62 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/22