Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10118
-gerrit
commit b60dbdbc728f2bb33e89e7dda3cd30ac9be37ab5 Author: Lee Leahy leroy.p.leahy@intel.com Date: Fri May 1 13:24:48 2015 -0700
DO NOT MERGE: FSP 1.1 disable BOOT_STATE_INIT_ENTRIES
Comment out BOOT_STATE_INIT_ENTRIES macros and corresponding routines to allow the FSP 1.1 driver to compile
BRANCH=none BUG=None TEST=Build and run on Braswell
Change-Id: I83f86507e77bf1ea1e8c761cbf945cd57badd89d Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/drivers/intel/fsp1_1/fsp_util.c | 2 ++ src/drivers/intel/fsp1_1/hob.c | 4 ++++ src/soc/intel/braswell/southcluster.c | 3 +++ src/soc/intel/braswell/spi.c | 2 ++ 4 files changed, 11 insertions(+)
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 105f46c..659cbaa 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -175,6 +175,7 @@ void fsp_notify(u32 phase) phase, status); }
+#if 0 /* LPL - BOOT_STATE_INIT_ENTRIES failing */ static void fsp_notify_boot_state_callback(void *arg) { u32 phase = (u32)arg; @@ -194,6 +195,7 @@ BOOT_STATE_INIT_ENTRIES(fsp_bscbs) = { fsp_notify_boot_state_callback, (void *)EnumInitPhaseReadyToBoot) }; +#endif /* 0 */
#endif /* #ifndef __PRE_RAM__ */
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 5722255..2e0e5ff 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -468,6 +468,8 @@ void __attribute__ ((weak)) update_mrc_cache(void *unused) } #endif /* CONFIG_ENABLE_MRC_CACHE */
+// TODO: Fix the error below, error processing macro with NULL +#if 0 // LPL static void find_fsp_hob_update_mrc(void *unused) { void *hob_list_ptr; @@ -489,3 +491,5 @@ static void find_fsp_hob_update_mrc(void *unused) /* Update the MRC/fast boot cache as part of the late table writing stage */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); + +#endif // 0 LPL diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 6db33b3..48a4b79 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -469,6 +469,7 @@ int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) return -1; }
+#if 0 /* LPL - BOOT_STATE_INIT_ENTRIES failing */ static void update_gnvs(device_t dev, int nvs_index, global_nvs_t *gnvs) {
@@ -545,3 +546,5 @@ BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL), }; +#endif /* 0 */ + diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 5f5939b..44a8e98 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -294,6 +294,7 @@ void spi_init(void) }
+#if 0 /* LPL - BOOT_STATE_INIT_ENTRIES failing */ static void spi_init_cb(void *unused) { spi_init(); @@ -302,6 +303,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +#endif /* 0 */
int spi_claim_bus(struct spi_slave *slave) {