[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports
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Patch Set 8:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@10 
PS8, Line 10: and jsl in fsp params.
Won't the TGL FSP also support PCH-H? It seems the new numbers are
for PCH-LP only.

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... 
PS8, Line 108: 	for (i = 0; i < CONFIG_SOC_INTEL_USB2_PORT_MAX; i++) {
How about `ARRAY_SIZE(params->PortUsb20Enable)` instead? It's always better
to use the target size to avoid writing to undefined memory.

We should, in any case, assert that we don't make wrong assumptions about
the UPDs. e.g. with the size as above:

_Static_assert(ARRAY_SIZE(params->PortUsb20Enable) <= ARRAY_SIZE(config->usb2_ports));

Then we were also sure that we don't read from undefined locations. This way
we wouldn't need more Kconfigs and would be safer.