ChrisEric1 CECL has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71999 )
Change subject: src/mainboard/dell/inspiron_*: Add Support for Dell Inspiron 620 & 3847 ......................................................................
src/mainboard/dell/inspiron_*: Add Support for Dell Inspiron 620 & 3847
Add Initial Support for Dell Inspiron 620 and Dell Inspiron 3847. (using Autoport) On my 620, UEFI freezes up for ~5m then boots, my 2nd RAM slot doesn't get recognized (even in stock rom, although stock doesn't boot up and gives freeze or POST), else everything works from what I can tell (could mean my board is partially damaged) On my 3847, everything works, UEFI doesn't freeze up, but my external GPU doesn't work (internal does), it is a NVIDIA GEFORCE GT 710 and cannot figure out how to default to it, though the linux driver works fine with it (windows was also untested on both machines). NOTE: As of 2022, I need to get a replacement 620 MB, due to the fact that the BIOS chip fried. My 3847 Works fine though. Someone also had the same freezing issue on a SNB in coreboot discord, which later upgraded to IVY Bridge, could also need a SATA Patch, not known yet until a get a new MB.
Change-Id: I17df5204e285055e7afb8a2545b0153994670e45 Signed-off-by: Christopher Lentocha christopherericlentocha@gmail.com --- A src/mainboard/dell/inspiron_3847/Kconfig A src/mainboard/dell/inspiron_3847/Kconfig.name A src/mainboard/dell/inspiron_3847/Makefile.inc A src/mainboard/dell/inspiron_3847/acpi/ec.asl A src/mainboard/dell/inspiron_3847/acpi/platform.asl A src/mainboard/dell/inspiron_3847/acpi/superio.asl A src/mainboard/dell/inspiron_3847/board_info.txt A src/mainboard/dell/inspiron_3847/bootblock.c A src/mainboard/dell/inspiron_3847/devicetree.cb A src/mainboard/dell/inspiron_3847/dsdt.asl A src/mainboard/dell/inspiron_3847/gma-mainboard.ads A src/mainboard/dell/inspiron_3847/gpio.c A src/mainboard/dell/inspiron_3847/hda_verb.c A src/mainboard/dell/inspiron_3847/romstage.c A src/mainboard/dell/inspiron_620/Kconfig A src/mainboard/dell/inspiron_620/Kconfig.name A src/mainboard/dell/inspiron_620/Makefile.inc A src/mainboard/dell/inspiron_620/acpi/ec.asl A src/mainboard/dell/inspiron_620/acpi/platform.asl A src/mainboard/dell/inspiron_620/acpi/superio.asl A src/mainboard/dell/inspiron_620/acpi_tables.c A src/mainboard/dell/inspiron_620/board_info.txt A src/mainboard/dell/inspiron_620/devicetree.cb A src/mainboard/dell/inspiron_620/dsdt.asl A src/mainboard/dell/inspiron_620/early_init.c A src/mainboard/dell/inspiron_620/gma-mainboard.ads A src/mainboard/dell/inspiron_620/gpio.c A src/mainboard/dell/inspiron_620/hda_verb.c A src/mainboard/dell/inspiron_620/mainboard.c 29 files changed, 1,091 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/71999/1
diff --git a/src/mainboard/dell/inspiron_3847/Kconfig b/src/mainboard/dell/inspiron_3847/Kconfig new file mode 100644 index 0000000..7dd1fec --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/Kconfig @@ -0,0 +1,28 @@ +if BOARD_DELL_INSPIRON_3847 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + +config MAINBOARD_DIR + string + default "dell/inspiron_3847" + +config MAINBOARD_PART_NUMBER + string + default "Inspiron 3847" + +config VGA_BIOS_ID + string + default "8086,0412" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/inspiron_3847/Kconfig.name b/src/mainboard/dell/inspiron_3847/Kconfig.name new file mode 100644 index 0000000..1d74972 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_INSPIRON_3847 + bool "Inspiron 3847" diff --git a/src/mainboard/dell/inspiron_3847/Makefile.inc b/src/mainboard/dell/inspiron_3847/Makefile.inc new file mode 100644 index 0000000..ec8ca22 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/inspiron_3847/acpi/ec.asl b/src/mainboard/dell/inspiron_3847/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/acpi/ec.asl diff --git a/src/mainboard/dell/inspiron_3847/acpi/platform.asl b/src/mainboard/dell/inspiron_3847/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/dell/inspiron_3847/acpi/superio.asl b/src/mainboard/dell/inspiron_3847/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/acpi/superio.asl diff --git a/src/mainboard/dell/inspiron_3847/board_info.txt b/src/mainboard/dell/inspiron_3847/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/inspiron_3847/bootblock.c b/src/mainboard/dell/inspiron_3847/bootblock.c new file mode 100644 index 0000000..1cec5c4 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/pch.h> + +/* FIXME: remove this if not needed */ +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/dell/inspiron_3847/devicetree.cb b/src/mainboard/dell/inspiron_3847/devicetree.cb new file mode 100644 index 0000000..b813b17 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/devicetree.cb @@ -0,0 +1,106 @@ +chip northbridge/intel/haswell # FIXME: check ec_present, usb_xhci_on_resume, gfx + register "ec_present" = "false" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "panel_cfg" = "{ + .up_delay_ms = 0, + .down_delay_ms = 0, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 0, + .backlight_off_delay_ms = 0, + .backlight_pwm_hz = 0, + }" + register "usb_xhci_on_resume" = "false" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "gpe0_en_1" = "0x20000046" + register "gpe0_en_2" = "0x0" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x11" + device pci 14.0 on # xHCI Controller + subsystemid 0x1028 0x0622 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1028 0x0622 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x0622 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1028 0x0622 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x0622 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x1028 0x0622 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1028 0x0622 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x0622 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1028 0x0622 + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1028 0x0622 + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x0622 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1028 0x0622 + end + device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 + subsystemid 0x1028 0x0622 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1028 0x0622 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1028 0x0622 + end + end +end diff --git a/src/mainboard/dell/inspiron_3847/dsdt.asl b/src/mainboard/dell/inspiron_3847/dsdt.asl new file mode 100644 index 0000000..e8c6e53 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + /* FIXME: remove this if the board doesn't have backlight. */ + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/inspiron_3847/gma-mainboard.ads b/src/mainboard/dell/inspiron_3847/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/inspiron_3847/gpio.c b/src/mainboard/dell/inspiron_3847/gpio.c new file mode 100644 index 0000000..bcb672c --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/gpio.c @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, + .gpio9 = GPIO_RESET_RSMRST, + .gpio10 = GPIO_RESET_RSMRST, + .gpio11 = GPIO_RESET_RSMRST, + .gpio12 = GPIO_RESET_RSMRST, + .gpio13 = GPIO_RESET_RSMRST, + .gpio14 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_RSMRST, + .gpio26 = GPIO_RESET_RSMRST, + .gpio27 = GPIO_RESET_RSMRST, + .gpio28 = GPIO_RESET_RSMRST, + .gpio29 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio40 = GPIO_RESET_RSMRST, + .gpio41 = GPIO_RESET_RSMRST, + .gpio42 = GPIO_RESET_RSMRST, + .gpio43 = GPIO_RESET_RSMRST, + .gpio44 = GPIO_RESET_RSMRST, + .gpio45 = GPIO_RESET_RSMRST, + .gpio46 = GPIO_RESET_RSMRST, + .gpio57 = GPIO_RESET_RSMRST, + .gpio58 = GPIO_RESET_RSMRST, + .gpio59 = GPIO_RESET_RSMRST, + .gpio60 = GPIO_RESET_RSMRST, + .gpio61 = GPIO_RESET_RSMRST, + .gpio62 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio72 = GPIO_RESET_RSMRST, + .gpio73 = GPIO_RESET_RSMRST, + .gpio74 = GPIO_RESET_RSMRST, + .gpio75 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/inspiron_3847/hda_verb.c b/src/mainboard/dell/inspiron_3847/hda_verb.c new file mode 100644 index 0000000..59f28a8 --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/hda_verb.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/inspiron_3847/romstage.c b/src/mainboard/dell/inspiron_3847/romstage.c new file mode 100644 index 0000000..9e6536b --- /dev/null +++ b/src/mainboard/dell/inspiron_3847/romstage.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + /* FIXME: check this */ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/dell/inspiron_620/Kconfig b/src/mainboard/dell/inspiron_620/Kconfig new file mode 100644 index 0000000..8ad48eb --- /dev/null +++ b/src/mainboard/dell/inspiron_620/Kconfig @@ -0,0 +1,34 @@ +if BOARD_DELL_INSPIRON_620 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default "dell/inspiron_620" + +config MAINBOARD_PART_NUMBER + string + default "Inspiron 620" + +config VGA_BIOS_ID + string + default "8086,0102" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/inspiron_620/Kconfig.name b/src/mainboard/dell/inspiron_620/Kconfig.name new file mode 100644 index 0000000..55f778f --- /dev/null +++ b/src/mainboard/dell/inspiron_620/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_INSPIRON_620 + bool "Inspiron 620" diff --git a/src/mainboard/dell/inspiron_620/Makefile.inc b/src/mainboard/dell/inspiron_620/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/inspiron_620/acpi/ec.asl b/src/mainboard/dell/inspiron_620/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/acpi/ec.asl diff --git a/src/mainboard/dell/inspiron_620/acpi/platform.asl b/src/mainboard/dell/inspiron_620/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/dell/inspiron_620/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/dell/inspiron_620/acpi/superio.asl b/src/mainboard/dell/inspiron_620/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/acpi/superio.asl diff --git a/src/mainboard/dell/inspiron_620/acpi_tables.c b/src/mainboard/dell/inspiron_620/acpi_tables.c new file mode 100644 index 0000000..e275965 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +/* FIXME: check this function. */ +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/inspiron_620/board_info.txt b/src/mainboard/dell/inspiron_620/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/inspiron_620/devicetree.cb b/src/mainboard/dell/inspiron_620/devicetree.cb new file mode 100644 index 0000000..9f23686 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/devicetree.cb @@ -0,0 +1,102 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00fc0a01" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1028 0x04ed + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x04ed + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1028 0x04ed + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x04ed + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1028 0x04ed + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x04ed + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1028 0x04ed + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1028 0x04ed + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x04ed + end + device pci 1f.5 on # SATA Controller 2 Unsupported PCI device 8086:1c08 + subsystemid 0x1028 0x04ed + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1028 0x04ed + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1028 0x04ed + end + end +end diff --git a/src/mainboard/dell/inspiron_620/dsdt.asl b/src/mainboard/dell/inspiron_620/dsdt.asl new file mode 100644 index 0000000..7d13c55 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/inspiron_620/early_init.c b/src/mainboard/dell/inspiron_620/early_init.c new file mode 100644 index 0000000..52a5ffe --- /dev/null +++ b/src/mainboard/dell/inspiron_620/early_init.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f01); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/inspiron_620/gma-mainboard.ads b/src/mainboard/dell/inspiron_620/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/inspiron_620/gpio.c b/src/mainboard/dell/inspiron_620/gpio.c new file mode 100644 index 0000000..32124ae --- /dev/null +++ b/src/mainboard/dell/inspiron_620/gpio.c @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, + .gpio9 = GPIO_RESET_RSMRST, + .gpio10 = GPIO_RESET_RSMRST, + .gpio11 = GPIO_RESET_RSMRST, + .gpio12 = GPIO_RESET_RSMRST, + .gpio13 = GPIO_RESET_RSMRST, + .gpio14 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, + .gpio24 = GPIO_RESET_RSMRST, + .gpio27 = GPIO_RESET_RSMRST, + .gpio28 = GPIO_RESET_RSMRST, + .gpio29 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio40 = GPIO_RESET_RSMRST, + .gpio41 = GPIO_RESET_RSMRST, + .gpio42 = GPIO_RESET_RSMRST, + .gpio43 = GPIO_RESET_RSMRST, + .gpio44 = GPIO_RESET_RSMRST, + .gpio45 = GPIO_RESET_RSMRST, + .gpio46 = GPIO_RESET_RSMRST, + .gpio57 = GPIO_RESET_RSMRST, + .gpio58 = GPIO_RESET_RSMRST, + .gpio59 = GPIO_RESET_RSMRST, + .gpio60 = GPIO_RESET_RSMRST, + .gpio61 = GPIO_RESET_RSMRST, + .gpio62 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio72 = GPIO_RESET_RSMRST, + .gpio74 = GPIO_RESET_RSMRST, + .gpio75 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/inspiron_620/hda_verb.c b/src/mainboard/dell/inspiron_620/hda_verb.c new file mode 100644 index 0000000..59f28a8 --- /dev/null +++ b/src/mainboard/dell/inspiron_620/hda_verb.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/inspiron_620/mainboard.c b/src/mainboard/dell/inspiron_620/mainboard.c new file mode 100644 index 0000000..4322c1e --- /dev/null +++ b/src/mainboard/dell/inspiron_620/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};