[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37865 )

Change subject: mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0
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Patch Set 4:

So I guess I'm misunderstanding something.  Does the kernel treat "opportunistic" S0ix differently from other entries into S0ix?  And so that's why this is needed?

The LPIT document https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.... doesn't say anything about this, and just says that the OSPM will call the _DSM function with 5 or 6 as the argument upon entering/exiting the S0 Idle state.