[coreboot-gerrit] Change in ...coreboot[master]: sb/intel/spi: Check for the SPI lock bit during runtime

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33388

Change subject: sb/intel/spi: Check for the SPI lock bit during runtime
......................................................................

sb/intel/spi: Check for the SPI lock bit during runtime

The SPI swseq controller can be locked in other parts of the code, for
instance when it's locked down in the finalize section. The driver
has to be made aware of that. The simpler solution is to not keep
track of the state and simply read out the lock bit on each SPI
transfer.

Change-Id: Ifcd5121b89d6f80fc1c1368786982d0d9fa1bf61
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/spi.c
1 file changed, 25 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33388/1

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index bf2a44c..3cecd4f 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -40,8 +40,6 @@

typedef struct spi_slave ich_spi_slave;

-static int g_ichspi_lock = 0;
-
 typedef struct ich7_spi_regs {
    uint16_t spis;
    uint16_t spic;
@@ -292,7 +290,6 @@
    	cntlr->data = (uint8_t *)ich7_spi->spid;
    	cntlr->databytes = sizeof(ich7_spi->spid);
    	cntlr->status = (uint8_t *)&ich7_spi->spis;
-		g_ichspi_lock = readw_(&ich7_spi->spis) & HSFS_FLOCKDN;
    	cntlr->control = &ich7_spi->spic;
    	cntlr->bbar = &ich7_spi->bbar;
    	cntlr->preop = &ich7_spi->preop;
@@ -302,7 +299,6 @@
    	ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
    	cntlr->ich9_spi = ich9_spi;
    	hsfs = readw_(&ich9_spi->hsfs);
-		g_ichspi_lock = hsfs & HSFS_FLOCKDN;
    	cntlr->hsfs = hsfs;
    	cntlr->opmenu = ich9_spi->opmenu;
    	cntlr->menubytes = sizeof(ich9_spi->opmenu);
@@ -334,6 +330,29 @@
    pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
 }

+static int spi_locked(void)
+{
+	uint8_t *rcrb; /* Root Complex Register Block */
+	uint32_t rcba; /* Root Complex Base Address */
+	ich9_spi_regs *ich9_spi;
+	ich7_spi_regs *ich7_spi;
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev = PCI_DEV(0, 31, 0);
+#else
+	struct device *dev = pcidev_on_root(31, 0);
+#endif
+	rcba = pci_read_config32(dev, 0xf0);
+	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
+	rcrb = (uint8_t *)(rcba & 0xffffc000);
+	if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
+		ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);
+	        return !!(readw_(&ich7_spi->spis) & HSFS_FLOCKDN);
+	} else {
+		ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
+	        return !!(readw_(&ich9_spi->hsfs) | HSFS_FLOCKDN) ;
+	}
+}
+
 static void spi_init_cb(void *unused)
 {
    spi_init();
@@ -405,7 +424,7 @@

trans->opcode = trans->out[0];
    spi_use_out(trans, 1);
-	if (!g_ichspi_lock) {
+	if (!spi_locked()) {
    	/* The lock is off, so just use index 0. */
    	writeb_(trans->opcode, cntlr->opmenu);
    	optypes = readw_(cntlr->optype);
@@ -550,7 +569,7 @@
    	 * in order to prevent the Management Engine from
    	 * issuing a transaction between WREN and DATA.
    	 */
-		if (!g_ichspi_lock)
+		if (!spi_locked())
    		writew_(trans.opcode, cntlr->preop);
    	return 0;
    }