Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86277?usp=email )
Change subject: soc/intel/pantherlake: Add ability to set SaGv work points ......................................................................
soc/intel/pantherlake: Add ability to set SaGv work points
Hook up SaGv work point UPDs.
BUG=none TEST=Boot to OS.
Signed-off-by: Bora Guvendik bora.guvendik@intel.com Change-Id: Ie38d007edc293727066f2bc9f67037e6fbe77aa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86277 Reviewed-by: Jérémy Compostella jeremy.compostella@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subratabanik@google.com --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Jérémy Compostella: Looks good to me, approved
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index e879fad..cd91e31 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -42,6 +42,14 @@ uint16_t region_mask[MAX_IBECC_REGIONS]; };
+/* SaGv gears */ +enum soc_intel_pantherlake_sagv_gears { + GEAR_AUTO = 0, + GEAR_1 = 1, + GEAR_2 = 2, + GEAR_4 = 4, +}; + enum soc_intel_pantherlake_power_limits { PTL_U_1_CORE, PTL_H_1_CORE, diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 5b96891..0c17d02 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -73,6 +73,11 @@ m_cfg->SaGvWpMask = config->sagv_wp_bitmap; else m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; + + for (size_t i = 0; i < HOB_MAX_SAGV_POINTS; i++) { + m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i]; + m_cfg->SaGvGear[i] = config->sagv_gear[i]; + } }
if (config->max_dram_speed_mts)