[coreboot-gerrit] Change in coreboot[master]: amd/agesa: Make BottomIo position configurable

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38472 )

Change subject: amd/agesa: Make BottomIo position configurable
......................................................................

amd/agesa: Make BottomIo position configurable

Some PCI peripherals, such as discrete VGA adapters, require a great
amount of memory mapped IO. This patch allows the user to select at
build time the bottom IO to leave enough space for such devices.

We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated. 0x80000000 has been successfully
boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb).

Signed-off-by: Mike Banon 
Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38472
Tested-by: build bot (Jenkins) 
Reviewed-by: Michał Żygowski 
---
M src/northbridge/amd/agesa/Kconfig
M src/northbridge/amd/agesa/family14/state_machine.c
M src/northbridge/amd/agesa/family15tn/state_machine.c
M src/northbridge/amd/agesa/family16kb/state_machine.c
4 files changed, 18 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michał Żygowski: Looks good to me, approved

diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index 19b62f2..1e0153b 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -19,6 +19,17 @@

if NORTHBRIDGE_AMD_AGESA

+config BOTTOMIO_POSITION
+	hex "Bottom of 32-bit IO space"
+	default 0x80000000
+	help
+	  If PCI peripherals with big BARs are connected to the system
+	  the bottom of the IO must be decreased to allocate such devices.
+
+	  Declare the beginning of the 128MB-aligned MMIO region.  This
+	  option is useful when PCI peripherals requesting large address
+	  ranges are present, for example, graphic cards.
+
 config CONSOLE_VGA_MULTI
    bool
    default n
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index db923c5..5b00408 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -48,6 +48,8 @@

void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
 {
+	Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000,
+			MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8;
 }

void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c
index 85bc258..439e15d 100644
--- a/src/northbridge/amd/agesa/family15tn/state_machine.c
+++ b/src/northbridge/amd/agesa/family15tn/state_machine.c
@@ -18,6 +18,8 @@

void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
 {
+	Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000,
+			MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8;
 }

void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c
index a279629..be9adaf 100644
--- a/src/northbridge/amd/agesa/family16kb/state_machine.c
+++ b/src/northbridge/amd/agesa/family16kb/state_machine.c
@@ -20,6 +20,9 @@
 {
    AGESA_STATUS status;

+	Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000,
+			MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8;
+
    if (CONFIG(ENABLE_MRC_CACHE)) {
    	status = OemInitResume(&Post->MemConfig.MemContext);
    	if (status == AGESA_SUCCESS)