Attention is currently required from: David Wu, Zhuohao Lee, Alan Huang. Hou-hsun Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 )
Change subject: mb/google/brya/var/brask: Set PL and PsysPL ......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brya/variants/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/59576/comment/afc7e4b3_2d2449d1 PS1, Line 18: { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 }, Those PL2/PL4 values look like coming from baseline config. Have you decided to use baseline or performance line config for Brask? Btw, from ADL MoW WW46 (doc#626774), the 442 45W SKU (which maps to PCI_DEVICE_ID_INTEL_ADL_P_ID_1) had some PD optimization relaxation. The PL2 is down to 95W, and PL4 is down to 125W, please update the settings for this SKU accordingly.
https://review.coreboot.org/c/coreboot/+/59576/comment/71ad9937_f9f45700 PS1, Line 23: { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135, 257 }, If the psys_pmax_power is not used at all, I think it's better to remove it to avoid confusion. The psys_pmax calculation is done by psys_imax_ma * volts_mv in variant_update_psys_power_limits(). Is my understanding correct?