7 Oct
2020
7 Oct
'20
6:55 p.m.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44493 )
Change subject: commonlib/storage/mmc: Add DS and DDR50 speed modes ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.c File src/commonlib/storage/mmc.c:
https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.c... PS2, Line 197: Increase
Yes, initially "SDHCI bus clock: 0. […]
Ah, it increases from reset default speed. Is this reset speed what `mmc_select_ds` would program?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a
Gerrit-Change-Number: 44493
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