[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default

[Maximilian Brune (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier.

Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email )

Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
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Patch Set 3:

(1 comment)

Patchset:

PS3:
> the change for picasso is still missing in this series; would be good to create a patch for that soc […]

CB:86598
But I am not sure about genoa. It is a bit more complicated on that SOC.