[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Don't use PCI operations on the pci_domain device

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27244

Change subject: nb/intel/sandybridge: Don't use PCI operations on the pci_domain device
......................................................................

nb/intel/sandybridge: Don't use PCI operations on the pci_domain device

The pci_domain just happens to have bus, device and function set to 0,
which is why to code works.

This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.

Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/sandybridge/northbridge.c
1 file changed, 11 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27244/1

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 8c2aaf3..56d3c49 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -152,26 +152,28 @@
     * 14fe00000   5368MB TOUUD
     */

+	struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+
    /* Top of Upper Usable DRAM, including remap */
-	touud = pci_read_config32(dev, TOUUD+4);
+	touud = pci_read_config32(mch, TOUUD+4);
    touud <<= 32;
-	touud |= pci_read_config32(dev, TOUUD);
+	touud |= pci_read_config32(mch, TOUUD);

/* Top of Lower Usable DRAM */
-	tolud = pci_read_config32(dev, TOLUD);
+	tolud = pci_read_config32(mch, TOLUD);

/* Top of Memory - does not account for any UMA */
-	tom = pci_read_config32(dev, 0xa4);
+	tom = pci_read_config32(mch, 0xa4);
    tom <<= 32;
-	tom |= pci_read_config32(dev, 0xa0);
+	tom |= pci_read_config32(mch, 0xa0);

printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
           touud, tolud, tom);

/* ME UMA needs excluding if total memory <4GB */
-	me_base = pci_read_config32(dev, 0x74);
+	me_base = pci_read_config32(mch, 0x74);
    me_base <<= 32;
-	me_base |= pci_read_config32(dev, 0x70);
+	me_base |= pci_read_config32(mch, 0x70);

printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);

@@ -190,7 +192,7 @@
    }

/* Graphics memory comes next */
-	ggc = pci_read_config16(dev, GGC);
+	ggc = pci_read_config16(mch, GGC);
    if (!(ggc & 2)) {
    	printk(BIOS_DEBUG, "IGD decoded, subtracting ");

@@ -210,7 +212,7 @@
    }

/* Calculate TSEG size from its base which must be below GTT */
-	tseg_base = pci_read_config32(dev, 0xb8);
+	tseg_base = pci_read_config32(mch, 0xb8);
    uma_size = (uma_memory_base - tseg_base) >> 10;
    tomk -= uma_size;
    uma_memory_base = tomk * 1024ULL;