Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46682 )
Change subject: nb/intel/haswell/finalize.c: Align with Broadwell ......................................................................
nb/intel/haswell/finalize.c: Align with Broadwell
Reorder register writes to match the locking order in Broadwell.
Tested on Asrock B85M Pro4, still boots and registers are still locked.
Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46682 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/finalize.c 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 22f9862..1600a42 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,12 +22,12 @@
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1UL << 31); MCHBAR32_OR(DMIVCLIM, 1UL << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); + MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
/* Read+write the following */ MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM);