Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... PS5, Line 142: set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
if you could see since SPT (SKL) we are using similar approach. […]
Yes, I can see that newer Intel code uses a similar approach. Trying to explain why code is correct by just referencing it doesn't work.
The question is WHY does it use to work, not which code also does it.
The following code does use CR0.CD=1: Linux kernel: arch/x86/kernel/cpu/mtrr/mtrr.c coreboot ramstage MTRR code: src/cpu/x86/mtrr/mtrr.c coreboot intel car code: soc/intel/common/block/cpu/car/cache_as_ram.S
If it would be that easy to set up MTRRs from within CAR, why wasn't it done in 7f8afe063139f6fc7076a3e4edf6093a953792dc ?
For my understanding the postcar frame needs to be filled with MTRRs, because you can only updated them after CAR has been disabled.