Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44196
to look at the new patch set (#8).
Change subject: mrc_cache: Update mrc_cache data in romstage ......................................................................
mrc_cache: Update mrc_cache data in romstage
Previously, we were writing to cbmem after memory training and then writing the training data from cbmem to mrc_cache in ramstage. We were doing this because we were unable to read/write to SPI simultaneously on older SIP chips. Now that newer chips allow for simultaneously reads and writes, we can move the mrc_cache update into romstage.
Updating spi driver Kconfig to set BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y if both BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y and BOOT_DEVICE_SPI_FLASH=y to bring the appropriate libraries into romstage.
BUG=b:150502246 BRANCH=None TEST=reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen shchen@google.com Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3 --- M src/drivers/elog/Makefile.inc M src/drivers/mrc_cache/mrc_cache.c M src/drivers/spi/Kconfig M src/include/region_file.h M src/lib/region_file.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/deltaur/variants/baseboard/Makefile.inc M src/mainboard/intel/strago/Kconfig 8 files changed, 122 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44196/8