Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35993 )
Change subject: cpu/x86: Add a prog_run hook to set up caching of XIP stages ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35993/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35993/5//COMMIT_MSG@16 PS5, Line 16: fine on at least model_1067x and model_6ex. I'm not an expert, but would feel safer with CD set. Unless there is some implicit invalidation ofc.
https://review.coreboot.org/c/coreboot/+/35993/5/src/cpu/x86/mtrr/xip_cache.... File src/cpu/x86/mtrr/xip_cache.c:
https://review.coreboot.org/c/coreboot/+/35993/5/src/cpu/x86/mtrr/xip_cache.... PS5, Line 48: base = ALIGN_DOWN(base, mtrr_mask_size); Move below the `if`, so we don't align down too far in the >max case?
With arbitrary bases, it could even make sense to align up.