Attention is currently required from: Arthur Heymans, Xiang W, ron minnich.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email )
Change subject: arch/riscv: Add SMP support for exception handler ......................................................................
Patch Set 8:
(5 comments)
File src/arch/riscv/payload.c:
https://review.coreboot.org/c/coreboot/+/68841/comment/34f6d4da_4d63e143 : PS2, Line 70: write_csr(mscratch, MACHINE_STACK_TOP());
maybe mention why we save it in a comment. […]
Done
File src/arch/riscv/trap_util.S:
https://review.coreboot.org/c/coreboot/+/68841/comment/d6dd5460_b6a1624f : PS1, Line 118: bnez sp, 1f
maybe add the same comment as above for more clarity while reading: […]
Done
File src/arch/riscv/trap_util.S:
https://review.coreboot.org/c/coreboot/+/68841/comment/4ab6d99d_727ca63f : PS2, Line 12: LOAD x3, 3 * REGBYTES(sp)
might be worth to note (in a comment) that x2 is the stack pointer otherwise it is not clear why we […]
Done
https://review.coreboot.org/c/coreboot/+/68841/comment/ece46dea_94257f94 : PS2, Line 103: # when exiting coreboot, write sp to mscratch
how do we make sure that nothing else writes to MACHINE_TOP_STACK after coreboot is jumping to paylo […]
we would need to setup a PMP region for the stack (and also for the code used inside the trap handler) to protect it from being used by an s-mode payload. Leave that for another day
https://review.coreboot.org/c/coreboot/+/68841/comment/8861b4b9_328ebbd9 : PS2, Line 105: bnez sp, 1f # sp == 0, trap come from current program
nit: […]
Done