[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs

[Filip Lewiński (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Krystian Hebel, Michał Kopeć, Michał Żygowski, Paul Menzel.

Filip Lewiński has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83727?usp=email )

Change subject: soc/intel/cannonlake: Hook up Intel TXT FSP UPDs
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Patch Set 6:

(1 comment)

File src/soc/intel/cannonlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/83727/comment/5cf5466a_7cba485f?usp... :
PS3, Line 152: 	m_cfg->ApStartupBase = 1; /* Set to non-zero, FSP does NULL check */
> [Replaced](https://review.coreboot.org/c/coreboot/+/83727/4.. […]

The change breaks builds for some models because of the conditional inline definition of stop_this_cpu()

```
    CC         romstage/cpu/x86/lapic/lapic_cpu_stop.o
src/cpu/x86/lapic/lapic_cpu_stop.c:51:6: error: redefinition of 'stop_this_cpu'
   51 | void stop_this_cpu(void)
      |      ^
src/include/cpu/x86/lapic.h:173:29: note: previous definition is here
  173 | static __always_inline void stop_this_cpu(void)
      |                             ^
1 error generated.
```

working on fixing it