[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/alderlake: Remove DDR5 override

[Tim Crawford (Code Review)]

Attention is currently required from: Jeremy Soller.

Hello Jeremy Soller,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/75135

to review the following change.

Change subject: soc/intel/alderlake: Remove DDR5 override
......................................................................

soc/intel/alderlake: Remove DDR5 override

This workaround can be removed now that SPD data can be read from the
EEPROM via SMBus.

Change-Id: Iedb8f48f70892497d19a7d1b6d8a544080b686e7
Signed-off-by: Jeremy Soller 
Signed-off-by: Tim Crawford 
---
M src/soc/intel/alderlake/meminit.c
1 file changed, 14 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/75135/1

diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index cbc2b5c..2874e40 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -217,22 +217,6 @@
    mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
 }

-#define DDR5_CH_DIMM_OFFSET(ch, dimm)        ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
-
-static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
-						 const struct mem_spd *spd_info)
-{
-	for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
-		for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
-			size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
-			mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] =
-				spd_info->smbus[ch].addr_dimm[dimm] << 1;
-		}
-	}
-	mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
-	mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
-}
-
 void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
    	 const struct mem_spd *spd_info, bool half_populated)
 {
@@ -258,14 +242,6 @@
    case MEM_TYPE_DDR5:
    	meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
    	dq_dqs_auto_detect = true;
-		/*
-		* TODO: Drop this workaround once SMBus driver in coreboot is updated to
-		* support DDR5 EEPROM reading.
-		*/
-		if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
-			ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
-			return;
-		}
    	break;
    case MEM_TYPE_LP4X:
    	meminit_lp4x(mem_cfg);