Shaunak Saha (shaunak.saha@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15325
-gerrit
commit 77a1a7a8e6cfd469917a8f530d0b9d83d71d43e4 Author: Shaunak Saha shaunak.saha@intel.com Date: Fri Jun 10 19:36:49 2016 -0700
intel/amenia: GPE routing for amenia
This patch sets the devicetree for gpe0_dw configuration and also confgigures the GPIO lines for SCI.EC_SCI_GPI is configured to proper value and the gpio_tier1_sci_en bit in acpi register is set by adding a dummy method in GPE scope.
BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt
Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- src/mainboard/intel/amenia/acpi/mainboard.asl | 6 ++++++ src/mainboard/intel/amenia/devicetree.cb | 9 +++++++++ src/mainboard/intel/amenia/ec.h | 5 ++--- src/mainboard/intel/amenia/gpio.h | 2 +- 4 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl index a679471..535360a 100644 --- a/src/mainboard/intel/amenia/acpi/mainboard.asl +++ b/src/mainboard/intel/amenia/acpi/mainboard.asl @@ -117,3 +117,9 @@ Scope (_SB.PCI0.LPCB) #include <drivers/pc80/tpm/acpi/tpm.asl> #include "ec.asl" } + +Scope(_GPE) +{ + /* Dummy method for the Tier 1 GPIO SCI enable bit */ + Method(_L0F, 0) {} +} diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f..711b96d 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -15,6 +15,15 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
+ # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., If this route changes then the affected GPE + # offset bits also needs to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index 91890fd..bfb7b13 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,9 +20,8 @@
#include <ec/google/chromeec/ec_commands.h>
-/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* 32 from GPE0a which is reserved + GPIO_11 for SCI */ +#define EC_SCI_GPI GPE0_DW1_11
#define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index 87d6190..48bc144 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -239,7 +239,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */ PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */ - PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, NONE), /* SOC_WAKE_SCI_N */ PAD_NC(GPIO_12, DN_20K), PAD_NC(GPIO_13, DN_20K),